The Assured Neuro-Symbolic Learning and Reasoning (ANSR) program aims to overcome the critical barriers that have hindered the realization of AI in safety and mission-critical autonomous systems. DARPA addresses two reasons for this. ''First, data-driven ML lacks transparency, interpretability, and robustness and has unsustainable computational and data needs. Second, traditional approaches to building intelligent applications and autonomous systems that rely on knowledge representations and symbolic reasoning can be assured but are not robust to the uncertainties encountered in the real world.'' Our research directly addresses these challenges by pioneering a novel neuro-symbolic AI framework that enhances 3D scene representation in autonomous drones, aligning with the core objectives of the ANSR initiative.

Our research enhances 3D scene representation and reasoning in autonomous drones by leveraging neuro-symbolic AI. Traditional methods for 3D scene representation relying on dense point clouds are data-inefficient and lack interpretability. We address this by integrating symbolic object models using the Universal Scene Description (USD) language. Our Neuro-Symbolic Conversion (NSC) framework automates object identification within point clouds, substitutes them with symbolic models, and validates these substitutions through visual comparison, improving data efficiency and reasoning for downstream scenarios understanding tasks efficiency.

The attached images illustrate our innovative approach, where object-wise point-cloud generation and symbolic representation in USD files create more interpretable and efficient 3D models. By matching objects using metrics such as Mean Squared Error (MSE) and Structural Similarity Index (SSIM), we ensure the accuracy and robustness of these symbolic models. This methodology significantly contributes to the development of trustworthy autonomous systems, aligning with the objectives of the ANSR program. Our research has been recognized and published in prestigious AI venues, including the AAAI Workshop and ICAA, underscoring its impact in the field.

The rapid evolution of semiconductor technology has propelled us into an era where System-on-Chip (SoC) designs and chiplet-based architectures are becoming increasingly complex. As we approach for compute advancement, the sheer scale of on-chip communication protocols, coupled with the intricate web of RTL (Register Transfer Level) blocks, presents unprecedented challenges in chip design. The growing sea of interconnected IP (Intellectual Property) cores has deepened, with advanced SoCs averaging around 205 IP blocks [as of 2023], making the design process more daunting than ever.

To keep pace with these complexities, the integration of AI into the design process has emerged as a crucial enabler. AI has the potential to revolutionize productivity, delivering a 20-25% increase in silicon and software development efficiency. This shift is not just a necessity but a strategic imperative for staying competitive in the semiconductor industry.

Our research in electronic design automation (EDA) is motivated by the need to overcome critical bottlenecks in modern chip design. AI plays a pivotal role in this endeavor, providing semiconductor designers with advanced tools that streamline the design process, enhance productivity, and reduce costs—factors that are increasingly vital in an industry characterized by growing complexity and financial pressures. We specifically address two major challenges in EDA. The first is the mining of message flow specifications, which is crucial for identifying and resolving communication protocol bugs in complex SoC designs. The second challenge involves optimizing design space exploration to mitigate bottlenecks in High-Level Synthesis (HLS) implementation. These efforts are aimed at advancing the efficiency and reliability of chip design in the current technological landscape.

The electronic design automation (EDA) community acknowledges the necessity of specification in system design and verification. An efficient and reliable set of specifications is the first step toward an efficient and reliable digital design. The lack of good quality specifications can cause catastrophes in various safety-critical and mission-critical architectures. Therefore, many endeavors have been carried out to determine the correct specifications for reactive systems. Still, none of them obliterated the need for further work in this domain. The advancement in ML algorithms specifically in the area of data mining and large language models (LLM) has opened new research avenues for specification mining.

Our contributions in the area of specification mining for SoC post-silicon validation are significant and ongoing. We initially developed a sequential pattern mining framework to generate specifications based on execution traces. Recognizing the limitations of this approach, particularly in handling the exponentially growing search space, we enhanced our methodology by incorporating SAT solver-based trace modeling. Additionally, we advanced this work through language modeling using BERT, applying large language models (LLMs) to further improve the accuracy and efficiency of our specifications. This remains an active area of research within our group. Our findings have been published in prestigious conferences such as TCAD (transaction), ICCD, ISQED, and MWSCAS.

High-Level Synthesis (HLS) is vital for converting high-level algorithmic descriptions into hardware designs. However, design space exploration (DSE) in reconfigurable systems presents a significant challenge due to the multi-objective optimization problem across conflicting parameters. Traditional methods, while effective, can be time-consuming and computationally expensive, often taking hours or days for even small designs.

To overcome these limitations, we developed an ML-based accelerator framework that combines deep neural networks (DNN) and quantum machine learning (QML). This framework enhances DSE by introducing trail evaluation and pruning based on user-defined thresholds, reducing exploration time by discarding less promising candidates early. Additionally, it requires minimal training data, making it computationally efficient and adaptable to scenarios with scarce resources. The resulting models are lightweight and green, offering a faster, more efficient design exploration process.

We are actively working to improve SoC/FPGA design, with a focus on creating compact, energy-efficient designs. The design space exploration challenge, as illustrated in the attached image, highlights the importance of proper usage of pragma and design parameters. These factors enable customization of the design for both speed and energy efficiency. This project is part of our broader Green AI Design initiative, where we explore various optimization strategies to develop AI solutions that are not only effective but also energy-efficient. Our work has been published in various conferences within the CAS community.